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USB97CFDC2-01
USB Floppy Disk Controller
FEATURES
3.3 Volt, Low Power Operation Complete USB Specification 1.1 Compatibility - Includes USB Transceiver - Based on an Enhanced Version of SMSC's Industry Proven USB97C100 USB Controller Complete System Solution Including USB Mass Storage Class Compliant Win98/2000 Driver and Firmware - Supports 640K, 720K, 1.44M, 1.2M Windows 98 J, and 1.2M NEC DOS 6.x Formats - Supports Both the UFI and SFF8070i Command Sets - Supports USB Mass Storage Compliant Bootable Floppy BIOS - 4ms Seek Times - USB 1.1 Compliance, Including Low Power Device Class SUSPEND Mode Operation and Power Control of Disk Drive - Disk Drive Feedback of Readiness Upon Power Re-Application Option - Option for Ultra High Performance Using Additional Caching SRAM - Support for Floppy Drive Power Control Contains SMSC's Industry Proven Floppy Disk Controller - Licensed CMOS 765B Floppy Disk Controller - Supports Single Normal or Three Mode Floppy Drives - Supports Vertical Recording Format and High Capacity Drives in User Written Firmware Applications - Detects All Overrun and Underrun Conditions - Sophisticated Power Control Circuitry (PCC) Including Multiple Powerdown Modes for Reduced Power Consumption Enhanced Digital Data Separator - 1 Mbps, 500 Kbps, 300 Kbps, 250 Kbps Data Rates - Programmable Precompensation Modes Intelligent Auto Power Management - <250A SUSPEND Current - <75mA Operating Current Integrated 32Kbyte Program ROM - Uses external 3 wire serial EEPROM provides storage for unique OEM identification and string descriptors and drive option settings. - 10 options for various drive parameters are externally selectable via serial EEPROM data. Optional External Program Memory Interface for Custom Applications - 32K Byte Code Space - Flash, SRAM, or EPROM Memory 4KB Internal Buffer SRAM for High Performance Operation Integrated 14.318 MHz Crystal Driver Circuit 100 pin TQFP lead-free RoHS compliant package (12.0 x 12.0 mm body) - 25% smaller body size than other 100 pin TQFP packages
ORDERING INFORMATION
Order Number: USB97CFDC2-MV-01X for 100 pin TQFP lead-free RoHS compliant package
SMSC DS - USB97CFDC2-01
Rev. 02-27-07
DATASHEET
80 ARKAY DRIVE, HAUPPAUGE, NY 11788 (631) 435-6000, FAX (631) 273-3123 Copyright (c) 2007 SMSC or its subsidiaries. All rights reserved. Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete information sufficient for construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product descriptions at any time without notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The provision of this information does not convey to the purchaser of the described semiconductor devices any licenses under any patent rights or other intellectual property rights of SMSC or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of SMSC's standard Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request. SMSC products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC's website at http://www.smsc.com. SMSC is a registered trademark of Standard Microsystems Corporation ("SMSC"). Product names and company names are the trademarks of their respective holders. SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE, AND ANY AND ALL WARRANTIES ARISING FROM ANY COURSE OF DEALING OR USAGE OF TRADE. IN NO EVENT SHALL SMSC BE LIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES; OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT; TORT; NEGLIGENCE OF SMSC OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY OF BUYER IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
SMSC DS - USB97CFDC2-01
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Rev. 02-27-07
DATASHEET
1
GENERAL DESCRIPTION
The USB97CFDC2-01 is an integration of an Enhanced Multi-Endpoint USB 1.1 Peripheral Controller, a 32K Byte Program ROM, and the SMSC Floppy Disk Controller used in many of its Super IO products, such as the FDC37C869. Special care in the design has been taken to assure the lowest possible system current draw (<250A) during SUSPEND mode operation. Provisions for external program Flash Memory up to 32K bytes for program storage is provided for customized applications. Several pins are provided for controlling external power control elements and sensing specialized drive functions. Individual manufacturers may provide their unique USB vendor and product IDs and descriptor strings via an external 3 wire serial EEPROM. Up to 16 different configuration options for various drive related parameters are provided by 4 external configuration input pins which can be read at power-on reset.
SMSC DS - USB97CFDC2-01
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Rev. 02-27-07
DATASHEET
TABLE OF CONTENTS
1 2 3 4 5 GENERAL DESCRIPTION .............................................................................................................................3 DESCRIPTION OF PIN FUNCTIONS ...........................................................................................................5 PIN CONFIGURATION...................................................................................................................................6 BLOCK DIAGRAM ..........................................................................................................................................7 PIN DESCRIPTIONS........................................................................................................................................8 5.1 6 7 8 9 10 BUFFER TYPE DESCRIPTIONS ....................................................................................................................11
CONFIGURATION OPTIONS......................................................................................................................12 BOARD TEST MODE OPERATION ...........................................................................................................14 DC PARAMETERS.........................................................................................................................................15 AC PARAMETERS.........................................................................................................................................17 USB PARAMETERS.......................................................................................................................................19 10.1 10.2 USB DC PARAMETERS.........................................................................................................................19 USB AC PARAMETERS.........................................................................................................................21
11
MECHANICAL OUTLINE ............................................................................................................................24
SMSC DS - USB97CFDC2-01
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DATASHEET
2
DESCRIPTION OF PIN FUNCTIONS
nTRK0 nRDATA nWDATA nDSO USB+ FD0/OPT0 FD4/IN0 FA0 FA4 FA8 FA12 nFRD ROMEN XTAL1/CLKIN TST_OUT FLOPPY DISK INTERFACE (14 Pins) nINDEX nWRTPRT DRVDEN0 DRVDEN1 nWGATE nHDSEL nMTR0 USB INTERFACE (4 Pins) USBAVDD EXTERNAL FLASH ROM INTERFACE (26 Pins) FD1/OPT1 FD2/OPT2 FD5/OUT0 FD6/OUT1 FA1 FA2 FA5 FA6 FA9 FA10 FA13 FA14 nFCE MISC (10 Pins) HDO nDRVRDY XTAL2 nRESET nTESTEN POWER, GROUNDS, and NO CONNECTS (46 Pins) nDSKCHG nSTEP nDIR
AGND FD3/OPT3 FD7/OUT2 FA3 FA7 FA11 FA15
nFDPWR nTEST
SMSC DS - USB97CFDC2-01
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DATASHEET
3
PIN CONFIGURATION
75 nDSKCHG DRVDEN1 N.C. GND N.C. GND VDD N.C. N.C. N.C. N.C. N.C. GND N.C. N.C. N.C. N.C. VDD N.C. N.C. N.C. N.C. N.C. N.C. N.C.
nRDATA nWRTPRT nTRK0 nINDEX nHDSEL nWGATE nWDATA nSTEP nDIR GND nDS0 nMTR0 DRVDEN0 AGND USB+ VDD USBAVDD FA11 FA9 FA8 FA13 FA14 GND N.C. 51 FA15 FA12 FA7 FA6 FA5 FA4 FA3 GND FA2 FA1 FA0 VDD FD0/OPT0 FD1/OPT1 FD2/OPT2 FD3/OPT3 FD4/IN0 FD5/OUT0 FD6/OUT1 FD7/OUT2 nFCE FA10 nFRD GND nFDPWR 25
USB97CFDC2-01 USB97CFDC2
1
SMSC DS - USB97CFDC2-01
N.C. N.C. N.C. N.C. N.C. N.C. N.C. GND N.C. N.C. N.C. N.C. N.C. VDD nTEST VDD XTAL1/CLKIN XTAL2 GND ROMEN nRESET TSTOUT N.C. HDO nDRVRDY
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DATASHEET
4
BLOCK DIAGRAM
To USB Bus
End Point Control
High Speed USB XCVR
Serial Interface Engine
Memory Management Unit
ROMEN
Map RAM
32K Byte Program ROM
CONTROL CLOCK SIE DMA RX/TX Queue
Arbiter
FD[7:0]/OPT[3:0] /IN0/OUT[2:0]
Flash/ SRAM Interface
FA[15:0] nFRD nFCE
4k Data Buffer RAM
8051 CPU 8237 Drive Control
nDRVRDY nHDO nFDPWR
GPIO
IRQ0
DRIVE INTERFACE
DRQ2 TC nDAK2
SA[13:0]
nTRK0, nINDEX, nWRTPRT, nDSKCHG nRDATA, DRVDEN0, DRVDEN1, nWDATA, nWGATE, nHDSEL, nDIR, nMTR0, nDS0, nSTEP
nIOW
FLOPPY DISK CONTROLLER
nIOR
nMEMW nMEMR SD[7:0]
SRAM Interface
nCE
ADDRESS DECODE
AEN
SMSC DS - USB97CFDC2-01
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DATASHEET
5
PIN DESCRIPTIONS
PIN NO. 75 NAME SYMBOL BUFFER TYPE DESCRIPTION
69
71
67
68
76
63
77 70
73
72
74
64
65
FLOPPY DISK INTERFACE Read Disk nRDATA IS Raw serial bit stream from the disk drive, low Data active. Each falling edge represents a flux transition of the encoded data. Write nWDATA OD12 This active low high current driver provides the encoded data to the disk drive. Each falling edge Data causes a flux transition on the media. This pin is high impedance when nRESET is active low. Head nHDSEL OD12 This high current output selects the floppy disk side for reading or writing. A logic "1" on this pin Select means side 0 will be accessed, while a logic "0" means side 1 will be accessed. . This pin is high impedance when nRESET is active low. Direction nDIR OD12 This high current low active output determines the direction of the head movement. A logic "1" on this Control pin means outward motion, while a logic "0" means inward motion. This pin is high impedance when nRESET is active low. Step Pulse nSTEP OD12 This active low high current driver issues a low pulse for each track-to-track movement of the head. This pin is high impedance when nRESET is active low. Disk Change nDSKCHG IS This input senses that the drive door is open or that the diskette has possibly been changed since the last drive selection. DRVDEN 0 DRVDEN 0 OD12 An active low on this pin indicates a disk drive spindle speed change from 300 RPM to 360 RPM or 1.2M format disks in three mode drives. This pin should be tied to the disk drives spindle speed control input pin. This pin is high impedance when nRESET is active low. DRVDEN 1 DRVDEN1 OD12 Reserved for future use. Write Gate nWGATE OD12 This active low high current driver allows current to flow through the write head. It becomes active just prior to writing to the diskette. This pin is high impedance when nRESET is active low. Track 0 nTRK0 IS This active low Schmitt Trigger input senses from the disk drive that the head is positioned over the outermost track. Index nINDEX IS This active low Schmitt Trigger input senses from the disk drive that the head is positioned over the beginning of a track, as marked by an index hole. Write Protect nWRTPRT IS This active low Schmitt Trigger input senses from the disk drive that a disk is write protected. Any write command is ignored. Motor On 0 nMTR0 OD12 This active low open drain output selects motor drive 0. This pin is high impedance when nRESET is active low. Drive Select 0 nDS0 OD12 This active low open drain output selects drive 0. This pin is high impedance when nRESET is active low.
SMSC DS - USB97CFDC2-01
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DATASHEET
PIN NO. 59 61
NAME USB Bus Data
SYMBOL USBUSB+
BUFFER TYPE
DESCRIPTION
58
62
USB Transceiver Supply USB Transceiver Ground
AVDD
USB INTERFACE IO-U These pins connect to the USB data signals through 33 ohm series resistors. The USB+ line should be pulled up with a 5%, 1.5K ohm resistor to indicate that this is a high speed USB device. This is the 3.3V supply to the internal USB transceiver. This is the supply ground for the internal USB transceiver.
AGND
38-35
34
33-31
50, 53, 54, 49, 57, 29, 56, 55, 4844, 42-40, 28 30
PROGRAM MEMORY INTERFACE FD[3:0]/ IO8 These signals are used to transfer data between Program the internal 8051 and the external program Memory Data OPT[3:0] memory when operating in external program Bus/Option memory mode (See ROMEN pin). When operating Select from internal program memory, the OPT3 pin must be tied high thru a resistor and the OPT[2:0] pins tied low thru a resistor (See configuration description section). These pins are not driven while the USB97CFDC2-01 is in SUSPEND mode and internal ROM mode is active. They are driven while in SUSPEND in external ROM mode.. FD4/IN0 IO8 This signal is used to transfer data between the Program internal 8051 and the external program memory Memory Data when operating in external program memory mode Bus/EEPROM (See ROMEN pin). When operating from internal Input program memory, this pin is the input data from an external serial EEPROM that contains manufacturer specific ID and string information, as required by the USB specification, and drive options. This pin is not driven while the USB97CFDC2-01 is in SUSPEND mode and internal ROM mode is active. It is driven while in SUSPEND in external ROM mode... FD[7:5]/ IO8 This signal is used to transfer data between the Program internal 8051 and the external program memory Memory Data OUT[2:0] when operating in external program memory mode Bus/EEPROM (See ROMEN pin). When operating from internal Output program memory, these pins are the output data and strobes to an external serial EEPROM that contains manufacturer specific ID and string information, as required by the USB specification, and drive options. These pins are driven while the USB97CFDC2-01 is in SUSPEND mode. Flash Memory FA[15:0] O8 These signals address memory locations within the Address Bus FLASH memory.
Flash Memory nFRD Read Strobe Flash Memory nFCE Chip Select XTAL1/ Crystal Input/External CLKIN Clock Input
O8 O8
Flash ROM Read; active low Flash ROM Chip Select; active low
17
MISCELLANEOUS ICLKx 14.318Mhz Crystal or clock input. This pin can be connected to one terminal of the crystal or can be connected to an external 14.318Mhz clock when a crystal is not used.
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SMSC DS - USB97CFDC2-01
DATASHEET
PIN NO. 18
20
24
25
26
21
22
15 16
14, 39, 60, 82, 93 8, 19, 27, 43, 52, 66, 79, 81, 88 1-7, 9-13, 23, 51, 78, 80, 83-87, 89-92, 94-100
DESCRIPTION 14.318Mhz Crystal This is the other terminal of the crystal, or left open when an external clock source is used to drive XTAL1/CLKIN. It may not be used to drive any external circuitry other than the crystal circuit. ROM Enable ROMEN IP If this input is tied high or left open, the internal program ROM is enabled. If tied low, external program memory can be used for custom applications. Drive Density HDO I In some configurations of the USB97CFDC, this Output drive pin indicates if a 640/720K disk is inserted in the drive. Polarity of this signal is determined by the configuration selected by the OPT[3:0] pins at reset. If this pin is not driven by the drive, it should be tied low. Drive Ready nDRVRDY I An active low signal on this pin from the floppy disk drive, after DS0 goes active, indicates that the system may activate MTR0. If the drive does not supply this signal, this pin should be tied low. Drive Power nFDPWR OD24 This active low signal is intended to activate an external power switch, either in the drive or on the system board, to supply power to the floppy disk drive. It is active whenever the USB97CFDC2-01 is not in SUSPEND mode. RESET input nRESET IS This active low signal is used by the system to reset the chip. The active low pulse should be at least 100ns wide. Test output TSTOUT O8 This signal is used for testing the chip via an internal XNOR chain. User should normally leave it unconnected. Test input nTEST I This signal is a manufacturing test pin. It should be tied to VDD for normal operation. Test Enable nTESTEN I This active low signal places the device into board test mode using the XNOR chain. For normal operation this pin should be tied high. See Board Test Mode Operation on page 14 POWER, GROUND, AND NO CONNECTS VDD +3.3V power OCLKx GND Ground Reference
NAME SYMBOL Crystal Output XTAL2
BUFFER TYPE
NC
No Connect. These pins should not be connected externally.
SMSC DS - USB97CFDC2-01
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DATASHEET
5.1
Buffer Type Descriptions
Table 1 - USB97CFDC2-01 Buffer Type Descriptions BUFFER DESCRIPTION I Input IP Input with 30uA pull-up IS Input with Schmitt trigger O8 Output with 8mA drive IO8 Input/output with 8mA drive IO8P Input/output with 8mA drive and 30uA pull-up OD12 Open drain....12mA sink O24 Output with 24mA drive OD24 Open drain....24mA sink ICLKx XTAL clock input OCLKx XTAL clock output I/O-U See Table 6.
SMSC DS - USB97CFDC2-01
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DATASHEET
6
CONFIGURATION OPTIONS
If ROMEN is tied high, then the internal ROM code is used for operation. If low, then an external memory on the FD bus is used for operational code. If the internal ROM is used, OPT3 must be tied high and OPT[2:0] must be tied low through a resistor. In this mode, an external serial EEPROM is used to store the OEM's USB assigned VID, their PID, their Product String, and the options for the particular drive connected to the USB97CFDC2-01. The data in the EEPROM is organized as follows: Note: If the data is not of the specified length, then fill the length with zeros, following the data. DEVICE DESCRIPTOR - 18 BYTES For a device with a VID/PID of 0424/0dc, the Device Descriptor looks like the one below. (Note that the data is separated by carriage returns in the "EEPROM.DAT" file. It is displayed here on a single line for clarity's sake.) The VID/PID occupy byte position 9 through 12. 12 0110 01 00 00 00 40 24 04 dc 0f 22 01 01 02 00 01 The data in bold are the VID and PID information. Note that the lo and the hi bytes are swapped, as in VendorLo, VendorHi, ProductLo and ProductHi.
LANGUAGE STRING - 4 BYTES String: 0409 (The language code for English) EEPROM.DAT: 04 03 09 04 (1st byte is the length, then the string ID, followed by the language ID in little endian.) MANUFACTURER STRING - 60 BYTES (UNICODE FORMAT) Example String: SMSC EEPROM.DAT: 3c 03 53 00 4d 00 53 00 43 00 ... 00 (1st byte is the length, followed by the string ID and the Unicode string itself in little endian.) PRODUCT STRING - 60 BYTES (UNICODE FORMAT) Example String: USB FDC EEPROM.DAT: 3c 03 55 00 53 00 42 00 20 00 46 00 44 00 43 00 ... 00 (Again the 1st byte is the length, followed by the string ID and the Unicode string itself in little endian.) SERIAL NUMBER STRING - 60 BYTES (UNICODE FORMAT) String: None EEPROM.DAT: 3c 03 4e 00 6f 00 6e 00 65 00 ... 00 (Again the 1st byte is the length, followed by the string ID and the Unicode string itself in little endian.)
INQUIRY DATA (IN RESPONSE TO A UFI_INQUIRY REQUEST) - 36 BYTES st Bytes 0 - 7: The values for the 1 8 bytes of the inquiry data come from Table 10 of the USB Mass Storage Class UFI Command Specification. For the USB floppy device, those bytes should be 00 80 00 01 1f 00 00 00. These bytes do not change. Bytes 8 - 15: Vendor Information (Example: SMSC) EEPROM.DAT: 53 4d 53 43 20 Bytes 16 - 31: Product Identification (Example: USB FDD) EEPROM.DAT: 55 53 42 20 46 44 44 20 Bytes 32 - 35: Product Revision Level (Example: 2.00) EEPROM.DAT: 32 2e 30 30
SMSC DS - USB97CFDC2-01
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DATASHEET
ATTRIBUTES - 4 BYTES (OBTAINED FROM SECTION 3.0) Example: The value for your drive from Table 3EEPROM.DAT: 00 05 00 00 ATTRIBUTES 0014 0000 C014 0004 0005 0000 0001 0000 0087 0000 8004 0002 000C 0000 020C 0000 802C 0000 33AC 0000 0005 0001 0405 0001 TAPE BITS Not set Set Not set Not set Not set Set Not set Not set Set Set Not set Not set HDO PIN HIGH 2HD 2DD 2DD N/A 2DD 2DD 2HD 2HD 2HD 2HD 2HD 2HD
Attributes
for
the
Variants
is
"0005
0000"
DRVRDY DELAY Before motor on Before motor on Before motor on Before motor on N/A Before motor on After motor on After motor on After motor on After motor on Before motor on Before motor on
DSKCHG DETECT Motor on Motor on Motor on Motor on Motor on Motor on Motor on Motor off Motor on Motor on Motor on Motor off
Notes: 1. The Tape Bits being set place the FDC Controller's data clock separator into a mode which has more spindle speed variation tolerance (for small form factor drives) but slightly less bit jitter tolerance. 2. 3. If the HDO pin is not provided use variant 0001 0000. The DRVRDY delay refers to either delaying the MOTOR ON command until DRVRDY goes active after power up ("Before motor on") or waiting after the motoro on command is given to the drive until DRVRDY is active before issuing a step command to the drive ("After motor on"). This applies only to drives with a DRVRDY pin. For those that do not, the DRVRDY input should be tied high (active) so that this delay is not used. The DSKCHG colum refers to whether the drive requires its motor to be on before it will update the DSKCHNG pin or not.
4.
To know more about the format of the Device Descriptor and the Strings please refer to the USB 1.1 Specifications. For information on the UFI Inquiry Data, please refer to the "USB Mass Storage Class UFI Command Specification".
SMSC DS - USB97CFDC2-01
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DATASHEET
7
BOARD TEST MODE OPERATION
By driving the nTESTEN pin low, the device will be placed into a special test mode to allow verification of attachment of the device to the circuit board. Every pin except the TSTOUT, XTAL2, and the power and ground pins become an input to an XNOR chain, as shown below, to allow continuity to be tested on the board. This test should individually toggle the state of the trace connected to the pin being examined for continuity, and the TSTOUT pin monitored for toggle of state. If no toggle occurs, either the pin under test is discontinuous, or the TSTOUT pin is not connected on the board
Pin1
Pin2
Pin3
Pin100 TSTOUT
SMSC DS - USB97CFDC2-01
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DATASHEET
8
DC PARAMETERS
MAXIMUM GUARANTEED RATINGS Operating Temperature Range........................................................................................................................... 0oC to +70oC Storage Temperature Range ............................................................................................................................-55o to +150oC Lead Temperature Range (soldering, 10 seconds) ..................................................................................................... +325oC Positive Voltage on any pin, with respect to Ground (Note 1) ................................................................................... Vcc+0.3V Negative Voltage on any pin, with respect to Ground......................................................................................................-0.3V Maximum Vcc ...................................................................................................................................................................+3.6V Note 1: Maximum voltage on all I type Inputs and the IS inputs, OD12 and OD24 outputs for floppy disk drive interface is 5.25V *Stresses above the specified parameters could cause permanent damage to the device. This is a stress rating only and functional operation of the device at any other condition above those indicated in the operation sections of this specification is not implied. Note 2: When powering this device from laboratory or system power supplies, it is important that the Absolute Maximum Ratings not be exceeded or device failure can result. Some power supplies exhibit voltage spikes on their outputs when the AC power is switched on or off. In addition, voltage transients on the AC power line may appear on the DC output. When this possibility exists, it is suggested that a clamp circuit be used.
DC ELECTRICAL CHARACTERISTICS (TA = 0C - 70C, Vcc = +3.3 V 10%) PARAMETER SYMBOL MIN TYP MAX UNITS COMMENTS I Type Input Buffer Low Input Level High Input Level ICLK Input Buffer Low Input Level High Input Level Input Leakage (All I and IS buffers) Low Input Leakage High Input Leakage O8 Type Buffer Low Output Level High Output Level Output Leakage I/O8(P) Type Buffer Low Output Level High Output Level Output Leakage IO8 IO8P
SMSC DS - USB97CFDC2-01
VILI VIHI 2.0
0.8
V V
TTL Levels
VILCK VIHCK 2.2
0.4
V V
IIL IIH
-10 -10
+10 +10
uA uA
VIN = 0 VIN = VCC
VOL VOH IOL 2.4 -10
0.4
V V
IOL = 8 mA IOH = -4 mA VIN = 0 to VCC (Note 1)
+10
UA
VOL VOH IOL IOL 2.4 -10 -50
Page 15
0.4
V V
IOL = 8mA IOH = -4mA VIN = 0 to Vcc (Note 1) VIN = 0 to Vcc (Note 1)
Rev. 02-27-07
+10 +10
A A
DATASHEET
PARAMETER OD12 Type Buffer Low Output Level Output Leakage O24 Type Buffer Low Output Level High Output Level Output Leakage OD24 Type Buffer Low Output Level Output Leakage IO-U Note 2 Supply Current Active Supply Current Standby
SYMBOL
MIN
TYP
MAX
UNITS
COMMENTS
VOL IOL -10
0.4 +10
V A
IOL = 12mA VIN = 0 to Vcc (Note 1)
VOL VOH IOL 2.4 -10
0.4
V V
IOL = 24mA IOH = -12mA VIN = 0 to Vcc (Note 1)
+10
A
VOL IOL -10
0.4 +10
V A
IOL = 24mA VIN = 0 to Vcc (Note 1)
ICC ICSBU
30 120
75 250
MA A
All outputs open.
Note 1: Output leakage is measured with the current pins in high impedance. Note 2: See Appendix A for USB DC electrical characteristics.
CAPACITANCE TA = 25C; fc = 1MHz; VCC = 3.3V LIMITS PARAMETER Clock Input Capacitance Input Capacitance Output Capacitance SYMBOL CIN CIN COUT MIN TYP MAX 20 10 20 UNIT TEST CONDITION pF All pins except USB pins (and pins under test tied pF to AC ground) pF
SMSC DS - USB97CFDC2-01
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DATASHEET
9
AC PARAMETERS
t1 t2 CLOCKI t2
FIGURE 1 - INPUT CLOCK TIMING
NAME t1 t2 tr, tf
Table 2 - Input Clock Timing Parameters DESCRIPTION MIN TYP Clock Cycle Time for 14.318MHz 69.84 Clock High Time/Low Time for 24MHz 41.9/ 27.9 Clock Rise Time/Fall Time (not shown)
MAX 27.9/ 41.9 5
UNITS ns ns ns
t1 FA [0:19 ]
t5
t3 FD[7:0
t4
nFRD t2
nFW R
FIGURE 2 - FLASH READ TIMING Table 3 - Flash Read Timing PARAMETER MIN FA[14:0] Address setup time to nFRD asserted 40 nFRD pulse width 110 FD[7:0] Data setup time to nFRD de-asserted 30 FD[7:0] Data hold time from nFRD de-asserted 0 FA[14:0] Address hold time from nFRD de-asserted 35
NAME t1 t2 t3 t4 t5
TYP
MAX
UNITS ns ns ns ns ns
SMSC DS - USB97CFDC2-01
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DATASHEET
nDIR
t3
t4 t1 nSTEP t2
nDS0
t5
nINDEX
t6
nRDATA
t7
nWDATA
t8
NAME t1 t2 t3 t4 t5 t6 t7 t8
PARAMETER nDIR Set Up to nSTEP Low nSTEP Active Time Low nDIR Hold Time After nSTEP nSTEP Cycle Time nDS0-1 Hold Time from nSTEP Low nINDEX Pulse Width nRDATA Active Time Low nWDATA Write Data Width Low
MIN
TYP 4 24 96 132 20 2 40 .5
MAX
UNITS X* X* X* X* X* X* ns Y*
*X specifies one MCLK period and Y specifies one WCLK period. MCLK = 16x Data Rate (at 500 Kbp/s MCLK = 8 MHz) WCLK = 2x Data Rate (at 500 Kbp/s WCLK = 1 MHz)
FIGURE 3 - DISK DRIVE TIMING
SMSC DS - USB97CFDC2-01
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DATASHEET
10 USB PARAMETERS
The following tables and diagrams were obtained from the USB specification
10.1 USB DC PARAMETERS
Minimum Differential Sensitivity (volts)
1.0
0.8
0.6
0.4
0.2
0.0 0.0
0.2 0.4
0.6
0.8 1.0
1.2
1.4
1.6 1.8
2.0
2.2 2.4
2.6
2.8 3.0
3.2
Common Mode Input Voltage (volts)
FIGURE 4 - DIFFERENTIAL INPUT SENSITIVITY OVER ENTIRE COMMON MODE RANGE
PARAMETER Supply Voltage Powered (Host or Hub) Port Supply Current Function Un-configured Function (in) Suspend Device Leakage Current Hi-Z State Data Line Leakage Input Levels Differential Input Sensitivity Differential Common Mode Range Single Ended Receiver Threshold Output Levels Static Output Low Static Output High Capacitance
SMSC DS - USB97CFDC2-01
Table 4 - DC Electrical Characteristics CONDITIONS SYMBOL (NOTE 1, 2) MIN VBUS ICC ICCINIT ICCS ILO Note 4 Note 5 4.4
TYP
MAX 5.25 100 100 100
UNIT V mA uA uA uA
0 V < VIN < 3.3 V |(D+) - (D-)|, and FIGURE 4 Includes VDI range
-10
10
VDI VCM VSE
0.2 0.8 0.8 2.5 2.0
V V V
VOL VOH
RL of 1.5 K to 3.6 V RL of 15 K to GND 2.8
0.3 (3) 3.6 (3)
V V
Page 19
Rev. 02-27-07
DATASHEET
PARAMETER Transceiver Capacitance Terminals Bus Pull-up Resistor on Root Port Bus Pull-down Resistor on Downstream Port Note 1: Note 2: Note 3: Note 4: Note 5:
SYMBOL CIN RPU RPD
CONDITIONS (NOTE 1, 2) Pin to GND (1.5 K +/- 5%) (15 K +/- 5%)
MIN
TYP
MAX 20 1.575 15.75
UNIT pF k k
1.425 14.25
All voltages are measured from the local ground potential, unless otherwise specified. All timing use a capacitive load (CL) to ground of 50pF, unless otherwise specified. This is relative to VUSBIN. This is dependent on block configuration set by software. When the internal ring oscillator and waiting for first setup packet.
SMSC DS - USB97CFDC2-01
Page 20
Rev. 02-27-07
DATASHEET
10.2 USB AC PARAMETERS
Rise Time CL Differential Data Lines 10% CL Full Speed: 4 to 20ns at C = 50pF L 90% 90% 10% Fall Time
tR
tF
FIGURE 5 - DATA SIGNAL RISE AND FALL TIME
TPERIOD Differential Data Lines
Crossover Points
Consecutive Transitions N * TPERIOD + TxJR1 Paired Transitions N * TPERIOD + TxJR2
FIGURE 6 - DIFFERENTIAL DATA JITTER
TPERIOD Differential Data Lines
Crossover Point
Crossover Point Extended
Diff. Data to SE0 Skew N * TPERIOD + TDEOP
Source EOP Width: TEOPT Receiver EOP Width: TEOPR1, TEOPR2
FIGURE 7 - DIFFERENTIAL TO EOP TRANSITION SKEW AND EOP WIDTH
SMSC DS - USB97CFDC2-01
Page 21
Rev. 02-27-07
DATASHEET
TPERIOD Differential Data Lines
TJR TJR1 TJR2
Consecutive Transitions N * TPERIOD + TJR1 Paired Transitions N * TPERIOD + TJR2
FIGURE 8 - RECEIVER JITTER TOLERANCE Table 5 - Full Speed (12Mbps) Source Electrical Characteristics CONDITIONS PARAMETER SYM (NOTE 1, 2, 3) MIN TYP MAX Driver Characteristics Transition Time: Rise Time Fall Time Rise/Fall Time Matching Output Signal Crossover Voltage Drive Output Resistance Data Source Timing Full Speed Data Rate TR TF TRFM VCRS ZDRV TDRATE Note 4,5 and FIGURE 5 CL = 50 pF CL = 50 pF (TR/TF)
UNIT
4 4 90 1.3 28 11.95
20 20 110 2.0 43 12.03
ns ns % V Mbs
Steady State Drive Ave. Bit Rate (12 Mb/s +/0.25%) Note 8 1.0 ms +/- 0.05% Note 6, 7 and FIGURE 6
Frame Interval Source Differential Driver Jitter To next Transition For Paired Transitions Source EOP Width Differential to EOP transition Skew Receiver Data Jitter Tolerance To next Transition For Paired Transitions EOP Width at receiver Must reject as EOP Must Accept
TFRAME
0.999 5
1.0005
ms
TDJ1 TDJ2 TEOPT TDEOP Note 7 and FIGURE 7 Note 7 and FIGURE 7 Note 7 and FIGURE 8
-3.5 -4.0 160 -2
3.5 4.0 175 5
ns ns ns ns
TJR1 TJR2 Note 7 and FIGURE 7 TEOPR1 TEOPR2
Page 22
-18.5 -9
18.5 9.0
ns ns
40 82
ns ns
Rev. 02-27-07
SMSC DS - USB97CFDC2-01
DATASHEET
PARAMETER
SYM
CONDITIONS (NOTE 1, 2, 3) (45 +/- 15%)
MIN 38.75
TYP
MAX 51.75 30
UNIT ns
Cable Impedance and Timing Cable Impedance (Full ZO Speed) Cable Delay (One Way) TCBL Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8:
All voltages are measured from the local ground potential, unless otherwise specified. All timing use a capacitive load (CL) to ground of 50pF, unless otherwise specified. Full speed timings have a 1.5K pull-up to 2.8 V on the D+ data line. Measured from 10% to 90% of the data signals. The rising and falling edges should be smoothly transiting (monotonic). Timing differences between the differential data signals. Measured at crossover point of differential data signals. These are relative to the 14.318 MHz crystal.
SMSC DS - USB97CFDC2-01
Page 23
Rev. 02-27-07
DATASHEET
11 MECHANICAL OUTLINE
FIGURE 9 - 100 PIN TQFP PACKAGE
A A1 A2 D D/2 D1 E E/2 E1 H L L1 e W R1 R2 ccc
MIN ~ 0.05 1.35 13.80 6.90 11.80 13.80 6.90 11.80 0.09 0.45 ~ 0 0.13 0.08 0.08 ~
o
NOMINAL ~ ~ 1.40 14.00 7.00 12.00 14.00 7.00 12.00 ~ 0.60 1.00 0.40 Basic 3.5o 0.16 ~ ~ ~
MAX 1.60 0.15 1.45 14.20 7.10 12.20 14.20 7.10 12.20 0.20 0.75 ~ 7o 0.23 ~ 0.20 0.08
REMARK Overall Package Height Standoff Body Thickness X Span 1 /2 X Span Measure from Centerline X body Size Y Span 1 /2 Y Span Measure from Centerline Y body Size Lead Frame Thickness Lead Foot Length from Centerline Lead Length Lead Pitch Lead Foot Angle Lead Width Lead Shoulder Radius Lead Foot Radius Coplanarity
Note 1: Controlling Unit: millimeter Note 2: Minimum space between protrusion and an adjacent lead is .007 mm. Note 3: Package body dimensions D1 and E1 do not include the mold protrusion. Maximum mold protrusion is 0.25 mm Note 5: Details of pin 1 identifier are optional but must be located within the zone indicated.
SMSC DS - USB97CFDC2-01
Page 24
Rev. 02-27-07
DATASHEET

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